1. Field of the Invention
The present invention relates to an array type multi-chip device in which a plurality of unit devices are arranged in an array and formed into a single composite chip, and more particularly to a fabrication method for forming external connection terminals thereof.
2. Description of the Conventional Art
Since electronic apparatuses have become miniaturized and intelligent, an array type multi-chip device has been commercialized. The array type multi-chip device is a multi-chip array type electronic component which is mounted on a substrate, in which at least two units of the same kind or different kinds of electronic components, such as a chip capacitor, a chip resistor, a chip inductor, a chip varistor, a chip bead, etc., are formed into a single composite device. According to the present invention, there is provided a surface-mounted array type multi-chip device which can be mounted in a miniaturized electronic apparatus and a fabrication method thereof, and in particular there is provided a fabrication method for an improved external connection terminal of the electronic apparatus.
First, to explain an example of a fabrication method for a conventional electronic component (a unit device), an electronic component device is fabricated in a well-known method as shown in FIG. 1A which illustrates a chip varistor. As shown therein, the chip varistor 10 is formed by alternately depositing multi-layer varistor members 11 and multi-layer internal electrodes 12 and then sintering the resultant structure, wherein parts of the internal electrodes 12 are exposed at one side surface of the chip varistor 10 and the other parts thereof are exposed at the opposite side surface of the chip varistor 10.
Next, as shown in FIG. 1B, external electrodes 13 are respectively formed at the both side surfaces of the chip varistor 10, that is, in contact with the exposed portions of the internal electrodes 12. The external electrodes 13 are formed by forming silver (Ag), palladium (Pd) or Ag--Pd powder into a paste, applying the paste to both side surfaces of the chip varistor 10 to cover the internal electrodes 12, drying the resultant structure at a temperature of 200.degree. under atmospheric pressure for about 15 minutes and then sintering the same at a temperature of 800.degree. for about 10 minutes.
As shown in FIG. 1C, nickel 14 is plated on outer surfaces of the external electrodes 13 and then a solder layer 15 formed of lead (Pb), tin (Sn) or Pb--Sn alloy is plated on the nickel 14.
A next example is illustrated for a case where a composite chip array type electronic component for which the electronic components which are fabricated as shown in FIGS. 1A through 1C, that is, various unit devices of the same kind or different kinds, are fabricated into a single chip.
In FIG. 2A, a plurality of unit devices 10 as shown in FIG. 1A, for example, four unit devices 10 are provided and arranged in an array and the array type unit devices 10 are sintered, thereby forming a single chip array sintered body 20. Accordingly, internal electrode groups 21a are exposed in as many as the number of the unit devices 10 at each of both side surfaces of the chip array sintered body 20. Here, each internal electrode group 21a is the plurality of internal electrodes 21 that each unit device 10 has.
Next, as shown in FIG. 2B, pastes 22 are applied on the internal electrode groups 21a and the resultant structure is sintered, thereby forming a plurality of external electrodes 22, the paste 22 being formed of a conductive material such as Ag, Pd or Ag--Pd. Next, as shown in FIG. 2C, nickel is plated on the external electrodes 22 and then a solder layer 23 formed of Pb, Sn or Pb--Sn alloy is plated on the nickel by electroplating or electroless plating.
However, the conventional fabrication method for the multi-chip device has the following problems. Specifically, in the process of plating the nickel and the solder layer onto the external electrodes, the plated film must be formed on the external electrodes 22. But, since surface resistance of the device (the sintered body) such as a chip inductor, a chip varistor, a chip LC filter, a chip bead or a chip capacitor is low and a structure thereof is finely formed, over-plating occurs, such that a surface of the chip is partially plated. Such an over plating definitely leads to shorting between neighboring terminals since the distance between the adjacent external electrodes 22 is considerably small.
Also, since the plating solution sticks to the surface of the chip device due to the over plating and thus penetrates into the chip, the electrical characteristics of the device can be changed which results in deterioration of the reliability of the device.
Further, since in the process for plating the surfaces of the external electrodes the plating solution which penetrates into the contact portions between the sintered body and the external electrodes reacts at the surface of the sintered body, thereby dissolving the surface of the sintered body, the contact surfaces between the external electrodes and the sintered body have excitation, thereby reducing the tensile strength of the external electrodes.
In addition, since the device and the external electrodes have low tensile strength, after being mounted on an electronic circuit substrate, the external terminals of the conventional multi-chip device slip off from the substrate, which results in poor electric contact between the circuit substrate and the electronic component.